This disclosure is related to data encoding and/or decoding for parallel busses.
As interfaces between components in computing platforms and/or between units within integrated circuits increase in transmission speed and/or bus width, noise and signal integrity issues increase in importance. For parallel data busses, for example data busses coupling memory devices to memory controllers, power supply variations and power supply noise may become issues due to relatively large changes in the ratio of ‘0’bits to ‘1’ bits on the bus in consecutive cycles. Further, power consumption may vary with changes to the ratio of ‘0’ bits to ‘1’ bits on the bus over a period of time.